This invention relates to an integrated circuit having data inputs and outputs and a control input which can switch the integrated circuit over between an operating state and a test state as a function of a control signal.
During ASIC (Application Specific Integrated Circuit) development, the manufacturer of an ASIC specifies a number of tests which the ASIC must satisfy. In order that these tests can be carried out, the ASIC must be switched to a test state in which the tests can be executed. In order that the ASIC has as few external terminals as possible, terminal pins for tests are combined with functional pins. In this way, a functional input or output pin can have the function of a test input or output pin. The state of the ASIC (operating state/test state) determines which function a pin has. In the normal operating state, the ASIC must never unintentionally be switched to the test state, and therefore the pin which switches the ASIC to the test state must not be shared. This switch-over is therefore performed by means of a separate test pin. This test pin is put at a fixed logic level during the normal operating state and at a different level during the test state. It can therefore no longer be used for the actual function of the ASIC.
FIG. 1 shows an ASIC which can be switched to a test state for a RAM test and a NAND tree test. In this ASIC, all of the data input pins Data (0) to Data (3) are each connected to a respective first input of a NAND of a NAND tree 4, to a first logic module 1 and to a respective input of a respective multiplexer of a multiplexer circuit 6, the second inputs of which are each connected to an output of the first logic module 1 and the outputs of which are each connected to an input of a RAM 3. The respective output of a NAND of the NAND tree 4 whose first input is connected to one of the data input pins is in each case connected to the second input of a further NAND, connected to an input pin, of the NAND tree 4. Like the data input pins Data (0) to Data (3), all of the further inputs of the integrated circuit are also connected to the NAND tree, whose output occupies a separate output pin of the integrated circuit. The output Dout of the RAM is connected to the input L2in of a logic module 2 and to an input of a multiplexer 7, the second input of which is connected to an output L2out of the logic module 2 and the output of which is connected to an output pin DataO (0). The logic modules 1 and 2 are supplied with a clock signal and a reset signal via input pins Clk and ResetX. The multiplexers are supplied, via an input pin TMin, with a signal TMode for switching over between the normal operating state and the test state.
Both a RAM test and a NAND tree test can be carried out in an integrated circuit constructed in this way. During the RAM test, all of the inputs and outputs of the ram are connected directly to input and output pins by the multiplexers present in the integrated circuit. As a result, the RAM can be tested independently of all the other assemblies present in the integrated circuit, by applying specific test patterns to the inputs and monitoring the output or outputs of the RAM in the process. The NAND tree test makes it possible to check whether the input or output pins connected to the NAND tree are actually connected to the integrated circuit. In order to test a specific input or output, all of the pins connected to the NAND tree are put at a specific potential, and the pin to be tested is switched over from this potential to a different potential. This switch-over can be observed at the output NAND-Treeout of the integrated circuit if the pin is actually connected to the integrated circuit. The response level of this tested pin can thus also be established as a function of the input level at which the output signal changes its level.
It may be asserted here that the implementation of these tests necessitates two pins which have no function in the operating state of the integrated circuit. These pins are the pin TMin for switching over to the test state and the pin NAND-Treeout, by means of which it is possible to establish the input level starting at which a specific pin of the integrated circuit responds. It is easy to see that these two pins are not dispensable, even though they are not required in the operating state of the integrated circuit. On the one hand, no other pin can assume the function of the input pin TMin, since all of the other input pins already have a function. On the other hand, unlike the output pin DataO (0), for example, the output pin NAND-Treeout cannot be multiplexed, since otherwise the input pin TMin for the switch-over signal TMode could not be checked by means of the NAND tree test.